`timescale 1ns / 1ps

`include "MIPSCPU_COMMON.vh"

module RegisterFile(
	rst,
	clk,
	read1_addr,
	value1,
	read2_addr,
	value2,
	write_enable,
	write_addr,
	written_value,
	zero_value,
	t0_value,
	t1_value,
	t2_value,
	t3_value,
	ra_value
    );

	input rst, clk;
	input[`REGISTER_ADDRESS_WIDTH - 1 : 0] read1_addr, read2_addr;
	output wire[`DATA_WIDTH - 1 : 0] value1, value2;
	input write_enable;
	input[`REGISTER_ADDRESS_WIDTH - 1 : 0] write_addr;
	input[`DATA_WIDTH - 1 : 0] written_value;
	output wire[`DATA_WIDTH - 1 : 0] zero_value, t0_value, t1_value, t2_value, t3_value, ra_value;
	
	reg[`DATA_WIDTH - 1 : 0] register_value[`MIPS_CPU_REGISTER_COUNT - 1 : 0];
	assign value1 = register_value[read1_addr];
	assign value2 = register_value[read2_addr];
	
	assign zero_value = register_value[`MIPS_CPU_REGISTER_ZERO_NO];
	assign t0_value = register_value[`MIPS_CPU_REGISTER_T0_NO];
	assign t1_value = register_value[`MIPS_CPU_REGISTER_T1_NO];
	assign t2_value = register_value[`MIPS_CPU_REGISTER_T2_NO];
	assign t3_value = register_value[`MIPS_CPU_REGISTER_T3_NO];
	assign ra_value = register_value[`MIPS_CPU_REGISTER_RA_NO];

	integer i;
	
	always @(negedge rst or negedge clk)
	begin
		if (!rst) begin
			for (i = 0; i < `MIPS_CPU_REGISTER_COUNT; i = i + 1)
				register_value[i] <= 0;
		end else if (!clk) begin
			if (write_enable && write_addr != `MIPS_CPU_REGISTER_ZERO_NO)
				register_value[write_addr] <= written_value;
		end
	end
	
endmodule
